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10 Results Found RTL design

Hidden Name

1-3y of Exp

Rtl design engineer India | 29 yrs. old

Hidden Name

Rtl design engineer
1-3y of Exp India 29 yrs. old
Working but looking for new opportunities
Verilog VHDL system verilog RTL Design RTL Coding RTL Verification +10 +14 +13

Hidden Name

10+y of Exp

Lecturer/Hardware Lab Supervisor Pakistan | 38 yrs. old

Hidden Name

Lecturer/Hardware Lab Supervisor
10+y of Exp Pakistan 38 yrs. old
Working but looking for new opportunities
I am able to design schematic; create components as well as PCB layout of any circuit on ‘EAGLE PCB Software. Assemble the PCB on mounted circuit board. Create new layouts or revisions as required. • Create schematic symbols, packages, device, and PCB footprint as per requirements. • Layout of simple to complex PCB's using best known design practices and manufacturing guidelines.Develop full documentation packages as required per work instructions I have vast experience in designing of Learning Trainers. Some of details are mentioned below: • Designed different types of Digital Logic Design Trainers for various Universities and Institutes as per Demands. Designed PIC Microcontroller Based Trainer Eagle PCB Proteus ISIS Xilinx ISE +2 +6 +5

Hidden Name

1-3y of Exp

UX Designer Saudi, Riyadh | 23 yrs. old

Hidden Name

UX Designer
1-3y of Exp Saudi, Riyadh 23 yrs. old
Unemployed. Looking for a job
UX Design User Experience Design User Research Wireframes Prototyping Figma +17 +21 +20
3,000 SAR / Monthly

Hidden Name

1-3y of Exp

Full-Stack Web Developer Egypt, Fayoum | 23 yrs. old

Hidden Name

Full-Stack Web Developer
1-3y of Exp Egypt, Fayoum 23 yrs. old
Unemployed. Looking for a job
HTML5 CSS3 JavaScript ES6+ Tailwind CSS React.js +19 +23 +22
3,000 SAR / Monthly

Hidden Name

1-3y of Exp

Digital Design & ASIC Engineer Egypt, Cairo | 24 yrs. old

Hidden Name

Digital Design & ASIC Engineer
1-3y of Exp Egypt, Cairo 24 yrs. old
Working but looking for new opportunities
RTL Design Digital Logic Functional Verification Static Timing Analysis (STA) Clock/Reset Domain Crossing (CDC/RDC) ASIC Flow +28 +32 +31
88 EUR / Monthly

Hidden Name

1-3y of Exp

Digital IC Design Engineer Egypt, Cairo | 23 yrs. old

Hidden Name

Digital IC Design Engineer
1-3y of Exp Egypt, Cairo 23 yrs. old
Working but looking for new opportunities
Verilog HDL VHDL RTL design FSMs memory architectures synchronous design +32 +36 +35

Hidden Name

1-3y of Exp

Hardware & RTL Design Engineer Egypt, Aswan | 25 yrs. old

Hidden Name

Hardware & RTL Design Engineer
1-3y of Exp Egypt, Aswan 25 yrs. old
Working but looking for new opportunities
SystemVerilog Verilog RTL Design FPGA ModelSim Quartus +2 +6 +5

Hidden Name

1-3y of Exp

Software Engineer Egypt, Alexandria | 29 yrs. old

Hidden Name

Software Engineer
1-3y of Exp Egypt, Alexandria 29 yrs. old
Unemployed. Looking for a job
C C++ Python DIO ADC PWM +24 +28 +27

Hidden Name

1-3y of Exp

Data Entry -Remote Egypt, Beni Suef | 23 yrs. old

Hidden Name

Data Entry -Remote
1-3y of Exp Egypt, Beni Suef 23 yrs. old
Unemployed. Looking for a job
Verilog SystemVerilog RTL design FSM FPGA Flow RISC-V Architecture +16 +20 +19

Hidden Name

1-3y of Exp

student Egypt, Cairo | 26 yrs. old

Hidden Name

student
1-3y of Exp Egypt, Cairo 26 yrs. old
Working but looking for new opportunities
VHDL C/C++ Python MATLAB Arduino RTL design +15 +19 +18